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// Verilog HDL for "Cam", "cam4mbx" "functional"
// **************************************************************
// * PROGRAM: cam4mbx *
// * *
// * FUNCTION: FPGA programm *
// * *
// * OPTIONS: - *
// **************************************************************
// * MODULE: cam4mbx *
// * *
// * FUNCTION: top-level module *
// * *
// **************************************************************
module cam4mbx( vsync,hsync,pclk,trig,dataframegrab,
datacamin,adclk,// Verilog HDL for "cam4mbx"
camclk, camres, phi1, phi2, resetcolumn, resetline,
rowaddr, rowsel, rowres, rowdat, coladdr, colsel,
sysclock,_sysreset,clockoutMBX,_hresetMBX,
bankoneaddr,bankonedata,bankonectr,
banktwoaddr,banktwodata,banktwoctr,Led
);
output vsync; // signals for frame grabber
output hsync;
output trig;
output pclk;
output[15:0] dataframegrab;
input [11:0] datacamin; // camera signals
output adclk;
output camclk;
output camres;
output phi1;
output phi2;
output resetcolumn;
output resetline;
output [9:0] rowaddr;
output rowsel;
output rowres;
output rowdat;
output [9:0] coladdr;
output colsel;
output [1:0] Led;
input sysclock; // system clock
input _sysreset; // system reset
input clockoutMBX; // clock form MBX-board
input _hresetMBX; // reset from MBx-board
output [17:0]bankoneaddr; //sram address first bank
output [15:0]bankonedata; //sram data
output [4:0] bankonectr; //memctr[0] = _CS
//memctr[1] = _UB
//memctr[2] = _LB
//memctr[3] = _WE
//memctr[4] = _OE
output [17:0]banktwoaddr; // second sram bank
output [15:0]banktwodata;
output [4:0] banktwoctr;
wire [15:0] datacamout;
wire [9:0] prerow;
wire div8clock;
wire div4clock;
wire div2clock;
wire pagerdy;
assign dataframegrab = datacamout;
assign banktwoaddr = 18'h0;
assign banktwodata = 16'h0;
assign banktwoctr = 5'b11111;
cam4nat cam(vsync,hsync,pclk,trig,datacamout,datacamin,adclk,
camclk,camres,phi1,phi2,resetcolumn,resetline,
rowaddr,rowsel,rowres,rowdat,coladdr,colsel,pagerdy,
10'd158,div4clock,_sysreset);
multidivider mul(div8clock,div4clock,div2clock,sysclock,_sysreset);
memwrite mem(bankoneaddr,bankonedata,bankonectr,sysclock,
datacamout,pagerdy,_sysreset);
blinker bln(Led,pagerdy,_sysreset);
endmodule
// Verilog HDL for "Cam", "cam4nat" "functional"
// **************************************************************
// * PROGRAM: cam4mbx *
// * *
// * FUNCTION: FPGA programm *
// * *
// * OPTIONS: *
// **************************************************************
// * MODULE: cam4nat *
// * *
// * FUNCTION: camera module driver *
// * *
// **************************************************************
module cam4nat(vsync,hsync,pclk,trig,
dataout, datain, adclk,
camclk, camres, phi1, phi2, resetcolumn, resetline,
rowaddr, rowsel, rowres, rowdat, coladdr, colsel,rowcountovl,
prerow, hiclock,_reset);
output vsync; //for frame grabbber card
output hsync;
output trig;
output pclk;
output [15:0] dataout; // image data output
input [11:0] datain; // image data input form camera-system
output adclk; // system clock
output camclk; // inverted system clock
output camres; // inverted system reset
output phi1; // correlated double sampling
output phi2; // correlated double sampling
output resetcolumn; // reset column line
output resetline; // NOT clock
output [9:0] rowaddr; // selects the actual row address
output rowsel; // enable signal for row address decoder for readout
output rowres; // enable signal for row address decoder for integration
output rowdat; // data signal for integration
output [9:0] coladdr; // selects the actual column address
output colsel; // enable signal for column address
output rowcountovl;
input [9:0] prerow; // size of integration rows
input hiclock; // external clock input
input _reset; // system reset
wire [11:0] datain;
wire [15:0] dataout;
wire [9:0] rowcounter; // row counter for readout
wire [9:0] colcounter; // column counter for readout
wire [9:0] prerow; // = (rowcountend) - (desired duration of intergration in rows)
wire clock; // internal used clock
wire _reset; // inverted system reset
wire colcountovl;
assign trig = 1'b0;
assign clock=hiclock; // clock connected to input hiclock
assign pclk = clock;
assign adclk = clock;
assign resetline = ~clock;
assign camclk = ~clock;
assign camres = _reset; // camera reset connected to inverted system reset
assign dataout = {4'h0, datain}; // image data output set to 0000+data input
counter co (rowcounter, colcounter, rowcountovl, colcountovl,
10'd287, 10'd503, 1'b0, clock, _reset);
syncer sy (vsync,hsync,rowcounter,colcounter,clock,_reset);
camdrv cd (phi1, phi2, resetcolumn, rowaddr, rowsel, rowres, rowdat,
coladdr, colsel, rowcounter, colcounter, rowcountovl, colcountovl,
prerow, /*prerow = (rowcountend) - (desired duration
of intergration in rows) */
10'd130, /*rowpreat = column for integration stop*/
10'd60, /*rowresat = column for integration start */
10'b0, /*rowselat = column for readout (rowselat < rowresat)*/
10'd142, /*colstart*/
10'd502, /*colstop*/
10'd288, /*rowcountend*/
clock, _reset);
endmodule
// Verilog HDL for "Cam", "camdrv" "functional"
// **************************************************************
// * PROGRAM: cam4mbx *
// * *
// * FUNCTION: FPGA programm *
// * *
// * OPTIONS: *
// **************************************************************
// * MODULE: camdrv *
// * *
// * FUNCTION: main function of camera module driver *
// * *
// **************************************************************
module camdrv(phi1, phi2, resetcolumn, rowaddr, rowsel, rowres, rowdat,
coladdr, colsel, rowcounter, colcounter, rowcountovl, colcountovl,
prerow, rowpreat, rowresat, rowselat,
colstart, colstop, rowcountend, clock, _reset);
output phi1;
output phi2;
output resetcolumn;
output [9:0] rowaddr;
output rowsel;
output rowres;
output rowdat;
output [9:0] coladdr;
output colsel;
input [9:0] rowcounter;
input [9:0] colcounter;
input rowcountovl, colcountovl;
input [9:0] prerow;
input [9:0] rowpreat;
input [9:0] rowresat;
input [9:0] rowselat;
input [9:0] colstart;
input [9:0] colstop;
input [9:0] rowcountend;
input clock;
input _reset;
reg [9:0] rowaddr;
reg [9:0] coladdr;
reg rowsel;
reg rowres;
reg rowdat;
reg colsel;
reg [9:0] rowaddrh;
reg [9:0] coladdrh;
reg rowselh;
reg rowresh;
reg rowdath;
reg colselh;
reg [9:0] precounter;
reg actcol;
reg phi1;
reg phi2;
reg rescolflag;
assign resetcolumn = rescolflag & ~clock;
always @(_reset)
begin
if (~_reset)
begin
assign rowaddr=0;
assign rowsel=0;
assign rowres=0;
assign rowdat=0;
assign coladdr=0;
assign colsel=0;
assign rowaddrh=0;
assign rowselh=0;
assign rowresh=0;
assign rowdath=0;
assign coladdrh=0;
assign colselh=0;
assign precounter=prerow;
assign actcol=0;
assign phi1=0;
assign phi2=0;
assign rescolflag=0;
end
else
begin
deassign rowaddr;
deassign rowsel;
deassign rowres;
deassign rowdat;
deassign coladdr;
deassign colsel;
deassign rowaddrh;
deassign rowselh;
deassign rowresh;
deassign rowdath;
deassign coladdrh;
deassign colselh;
deassign precounter;
deassign actcol;
deassign phi1;
deassign phi2;
deassign rescolflag;
end
end
always @(posedge clock)
begin
precounter <= (precounter==rowcountend)? 0 :
(rowcountovl)? prerow :
(colcountovl)? precounter+1 : precounter;
// counter for integration
// precounter = 0 if end of page reached
// prerow if last column in last row reached
// +1 if last column reached
rowselh <= (colcounter==rowselat);
// enable signal for row address decoder for readout
// goes high at column X
rowdath <= (colcounter==rowresat);
// data signal for integration
// goes high at column Z
rowresh <= ((colcounter==rowresat) | (colcounter==rowpreat));
// enable signal for row address decoder for integration
rowaddrh <= ((colcounter==rowselat) | (colcounter==rowresat))? rowcounter :
(colcounter==rowpreat)? precounter : rowaddrh;
// rowaddr = rowcounter if column = rowselat OR rowresat
// precounter if column = rowpreat
rowaddr <= rowaddrh; // one clock tick delay
rowsel <= rowselh;
rowdat <= rowdath;
rowres <= rowresh;
actcol <= (colcounter==colstart) | (actcol & ~(colcounter==colstop));
colselh <= actcol;
coladdrh <= actcol? (colcounter-colstart-1) : 3;
coladdr <= coladdrh; // one clock delay
colsel <= colselh;
phi1 <= ((colcounter== 6) | phi1) & ~(colcounter== 60);
phi2 <= ((colcounter==66) | phi2) & ~(colcounter==502);
rescolflag <= (colcounter==3) | (colcounter==63);
end
endmodule
// Verilog HDL for "Cam", "counter" "functional"
// **************************************************************
// * PROGRAM: cam4mbx *
// * *
// * FUNCTION: FPGA programm *
// * *
// * OPTIONS: *
// **************************************************************
// * MODULE: counter *
// * *
// * FUNCTION: increment colums and rows *
// * for readout *
// **************************************************************
module counter (rowcounter, colcounter, rowcountovl, colcountovl,
rowcountend, colcountend, countovlpol, clock, _reset);
output [9:0] rowcounter;
output [9:0] colcounter;
output rowcountovl;
output colcountovl;
input [9:0] rowcountend;
input [9:0] colcountend;
input countovlpol;
input clock;
input _reset;
reg [9:0] rowcounter;
reg [9:0] colcounter;
reg rowcountovl;
reg colcountovl;
always @(_reset)
begin
if (~_reset)
begin
assign rowcounter = 0;
assign colcounter = 0;
assign rowcountovl = countovlpol;
assign colcountovl = countovlpol;
end
else
begin
deassign rowcounter;
deassign colcounter;
deassign rowcountovl;
deassign colcountovl;
end
end
always @(posedge clock)
begin
rowcounter <= (colcounter==colcountend)?
((rowcounter==rowcountend)? 0 : rowcounter+1) : rowcounter;
// if column counter reached end, increment row +1
// if image page reached end, set to 0
colcounter <= (colcounter==colcountend)? 0 : colcounter+1;
// increment +1
// if end of row reached, set to 0
rowcountovl <= countovlpol ^ (colcounter==(colcountend-1) & rowcounter==rowcountend);
// rowcountovl = 1 if last column in last row reached else 0
colcountovl <= countovlpol ^ (colcounter==(colcountend-1));
// colcountovl = 1 if last colunm in row reached else 0
end
endmodule
// Verilog HDL for "Cam", "syncer" "functional"
// **************************************************************
// * PROGRAM: cam4mbx *
// * *
// * FUNCTION: FPGA programm *
// * *
// * OPTIONS: *
// **************************************************************
// * MODULE: syncer *
// * *
// * FUNCTION: for framegrabber *
// * *
// **************************************************************
module syncer(vsync, hsync, row, col, clock, _reset);
output vsync;
output hsync;
input [9:0] row;
input [9:0] col;
input clock;
input _reset;
reg vsync;
reg hsync;
always @(_reset)
begin
if (~_reset)
begin
assign vsync=0;
assign hsync=0;
end
else
begin
deassign vsync;
deassign hsync;
end
end
always @(posedge clock)
begin
vsync <= (row==0);
hsync <= (col==8);
end
endmodule
// Verilog HDL for "Cam", "memwrite" "functional"
// **************************************************************
// * PROGRAM: cam4mbx *
// * *
// * FUNCTION: FPGA programm *
// * *
// * OPTIONS: *
// **************************************************************
// * MODULE: memwrite *
// * *
// * FUNCTION: writes the sram *
// * *
// **************************************************************
module memwrite(memaddr,memdataout,memctr,sysclock,datain,pagerdy,_sysreset);
output[17:0] memaddr;
output[15:0] memdataout;
output[4:0] memctr; //memctr[0] = _CS
//memctr[1] = _UB
//memctr[2] = _LB
//memctr[3] = _WE
//memctr[4] = _OE
input sysclock;
input [15:0] datain;
input pagerdy;
input _sysreset;
reg [2:1] clockcounter; // divides divclock in sections of sysclock
reg [17:0] memaddr; // temporarily store memory-address
reg [15:0] memdataout; // temporarily store memory-data
reg [4:0] memctr;
always @(_sysreset)
begin
if (~_sysreset)
begin
assign clockcounter = 0;
assign memaddr = 0;
assign memdataout = 0;
assign memctr = 5'b11111; //_CS,_UB,_LB,_WE,OE
end
else
begin
deassign clockcounter;
deassign memaddr;
deassign memdataout;
deassign memctr;
end
end
always @(posedge sysclock)
begin
if(_sysreset)
begin
case(clockcounter)
0 : begin
memdataout <= datain;
end
1 : begin
memctr = 5'b00001;
end
2 : begin
memctr = 5'b00011;
end
3 : begin
if (pagerdy)
begin
memaddr <= 0;
end
else
begin
memaddr = memaddr +1;
end
end
endcase
clockcounter <= clockcounter +1;
end
end
endmodule
// Verilog HDL for "Cam", "multidivider" "functional"
// **************************************************************
// * PROGRAM: cam4mbx *
// * *
// * FUNCTION: FPGA programm *
// * *
// * OPTIONS: *
// **************************************************************
// * MODULE: multidivider *
// * *
// * FUNCTION: *
// * *
// **************************************************************
module multidivider(div8clock,div4clock,div2clock,clock,_reset);
output div8clock;
output div4clock;
output div2clock;
input clock;
input _reset;
clockdivider c1(div2clock,clock,_reset);
clockdivider c2(div4clock,div2clock,_reset);
clockdivider c3(div8clock,div4clock,_reset);
endmodule
// Verilog HDL for "Cam", "clockdivider" "functional"
// **************************************************************
// * PROGRAM: cam4mbx *
// * *
// * FUNCTION: FPGA programm *
// * *
// * OPTIONS: *
// **************************************************************
// * MODULE: clockdivider, multidivider *
// * *
// * FUNCTION: devides the clock *
// * *
// **************************************************************
module clockdivider (outclock,inclock,_reset);
input inclock;
input _reset;
output outclock;
reg outclock;
always @(_reset)
begin
if (~_reset)
begin
assign outclock = 0;
end
else
begin
deassign outclock;
end
end
always @(posedge inclock)
begin
outclock <= ~outclock;
end
endmodule
// Verilog HDL for "Cam", "blinker" "functional"
// **************************************************************
// * PROGRAM: cam4mbx *
// * *
// * FUNCTION: FPGA programm *
// * *
// * OPTIONS: *
// **************************************************************
// * MODULE: blinker *
// * *
// * FUNCTION: for LEDs *
// * *
// **************************************************************
module blinker(Led,pagerdy,_sysreset);
output[1:0] Led;
input pagerdy;
input _sysreset;
reg [7:0] ledcounter; //Counter for blinking LED
reg [1:0] Led;
always @(_sysreset)
begin
if (~_sysreset)
begin
assign Led = 3'b00;
assign ledcounter = 0;
end
else
begin
assign Led ={ledcounter[7],ledcounter[6]};
deassign ledcounter;
end
end
always @(posedge pagerdy)
begin
if (_sysreset)
begin
ledcounter <= ledcounter +1;
end
end
endmodule
Thorsten Thormaehlen
2000-03-28